1. Field of the Invention
This invention relates to generally to host adapters for interfacing between I/O buses, and in particular to storage configurations in multi-tasking host adapters.
2. Description of Related Art
Prior single chip host adapters have been single task devices. For example, U.S. Pat. No. 5,659,690, entitled "Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor," issued on Aug.19, 1997 to Stuber et al., which is incorporated herein by reference, had a single data channel connecting a SCSI bus with a host computer bus. An on-chip RISC processor, sometimes called a sequencer, managed all of the modules on the chip through a set of registers.
This host adapter was multi-tasking in the sense that multiple commands, each for a different SCSI target, could be in process at any given time. However, hardware in the host adapter could execute only one task at a time, such as transferring data from one SCSI target to the host computer. The sequencer managed the one task until either completion or interruption of the task. Upon completion or interruption of the task, the sequencer disabled the hardware and then reconfigured the hardware for a different task.
Since the hardware on the host adapter chip could execute only one task at a time, the sequencer on the chip managed only the one active task at a time. Consequently, there were long periods of time in which the sequencer was idle and waiting for an event such as the end of the data transfer. While the sequencer was capable of performing other tasks, the hardware limitations made such performance unusable.
A subsequent host adapter integrated circuit had two independent data channels that were managed by a single sequencer. One of the data channels could be transferring data between the host computer and SCSI buses, while the other of the data channels could be transferring administrative data such as I/O command blocks, scatter/gather lists, or command completions notifications to or from the host computer. In this host adapter integrated circuit, rather than wait for an event associated with one of the two data channels, the sequencer waited in an idle loop for an event in either to the two data channels. This permitted the sequencer to concurrently supervise active tasks in both the channels, and to provide timely service when required.
In this host adapter integrated circuit, each channel had its own unique set of registers, and also shared a set of registers common to both channels. Each unique set of registers had its own logical address space. This required two different sets of firmware routines for the sequencer, one associated with each channel, for tasks that were common to both channels, e.g., data transfers. While this host adapter integrated circuit was an improvement over the earlier one, the unique register set for each channel limited the expansion of the architecture unless space on the chip was allocated for a larger address space, which in turn required a larger command line for the sequencer, and more storage space for the command lines themselves.